This invention relates to insulated gate field-effect transistors (hereinafter referred to as "MOS FETs", when applicable), and more particularly to the structure of a semiconductor device including high voltage high current MOS FETs which can be effectively employed for integrated circuits.
With progress of the technique of semiconductor, integrated circuits have been improved in the degree of integration and in miniaturization, while formation of ordinary logic circuit MOS FETs and high voltage MOS FETs on one and the same substrate has been tried, as a result of which the development of high voltage MOS FETs has made remarkable progress.
High voltage MOS FETs should be formed especially with the following three phenomena taken into consideration:
(1) Punch-through between the source and the drain;
(2) Dielectric breakdown between the gate electrode and the drain region; and
(3) Avalanche caused by the electric field being concentrated near the junction of the drain region.
In order to eliminate these difficulties, a variety of methods have been proposed in the art. Among these methods, the following method is most effective: In the vicinity of the gate electrode where electric lines of force are likely to be concentrated under voltage application, offset regions low in impurity concentration are provided near the junctions of the source and drain regions so that the gate electrode is sufficiently spaced from the regions for prevention of the dielectric breakdown, and in the vicinity of the surface thereof the electric field strength of the junction is released.
This offset structure is, in general, a so-called "both offset structure" in which two offset regions are provided for the source region and the drain region, respectively. A method of forming high voltage MOS FETs withstanding a several tens of volts and ordinary logic circuit MOS FETs on one and the same substrate without changing the manufacturing steps has been proposed in Japanese Patent Application No. 174030/1986.
One example of the method will be described with reference to FIGS. 5(a) and 5(b). FIG. 5(a) is a plan view showing a part of a both offset structure high voltage MOS FETs pattern, and FIG. 5(b) is a sectional view taken along line C--C' in FIG. 5(a).
As shown in FIGS. 5(a) and 5(b), a MOS FET 50 comprises: an N.sup.+ type source region 52 and an N.sup.+ type drain region 53 which are formed in a P type semiconductor substrate 51; and a gate electrode 55 formed on a gate insulation film 54. In the MOS FET 50, insulation films 56 and 56' are formed between the gate insulation film 54 and the source region 52 and the drain region 53 by the LOCOS method (hereinafter referred to as "LOCOS insulation films", when applicable) and offset regions 57 and 57' are formed below the LOCOS insulation films 56 and 56', respectively. The offset regions are equal in conductivity type to the source and drain regions and are low in impurity concentration. In FIG. 5(a), the LOCOS insulation films 56 and 56' are not shown, and reference numerals 59 and 61 designate a source electrode and a drain electrode, respectively.
The provision of the LOCOS insulation films 56 and 56' and the offset regions 57 and 57' makes it possible to increase the distance between the source region and the drain region, to reduce the effect of the electric field which is liable to concentrate in the surface of the semiconductor substrate near the junctions of the two regions and the gate electrode 55, and to increase the sustaining voltage of the FET.
The LOCOS insulation films and the offset regions can be formed in nearly the same manufacturing steps as separating LOCOS insulating films and low impurity concentration layers as channel stoppers, respectively in the ordinary logic circuit MOS FETs; that is, they can be formed without increasing the number of manufacturing steps.
On the other hand, in order to increase the degree of integration in integrated circuits, it is essential to increase MOS FET sustaining voltage, and to permit, for instance in the case where a high voltage MOS FET pattern is formed, a current as large as possible to flow in a small area.
For this purpose, it is necessary to reduce an "on resistance (R.sub.ON)" with maintaining the sustaining voltage of the FET unchanged. The "on resistance (R.sub.ON)" as used herein is intended to mean the resistance between the source and drain regions provided when the MOS FET is rendered conductive. The "on resistance R.sub.ON)" of the high voltage MOS FET consists of a channel resistance and an offset region resistance. The channel resistance is determined from the dimensions of the MOS FET; i.e., the length and width of the channel region, and the threshold voltage; that is, it is substantially impossible to change the channel resistance. On the other hand, the offset region resistance depends on the size and the impurity concentration of the offset region; however, in order to maintain the sustaining voltage unchanged, the impurity concentration should not be increased so much.